Integrated circuit memories include static random access memory (SRAM). Many SRAM cell structures utilize six-transistor or eight-transistor memory cells. The large layout areas associated with such six-transistor and eight-transistor memory cells which are used in many implementations of SRAM cells has limited the design of high density SRAM devices.
Given these drawbacks, there have been attempts to build a thyristor-based memory cell with a simple layout and reduced layout area in comparison to conventional memory cells. A thrysitor is a bi-stable, three terminal device which consists of a four layer structure including a P-type anode region, an N-type base region, a P-type base region coupled to a gated electrode, and an N-type cathode region arranged in a PNPN configuration. PN junctions are formed between the P-type anode region and the N-type base region, between the N-type base region and the P-type base region, and between the P-type base region and the N-type cathode region. Contacts are made to the P-type anode region, the N-type cathode region, and the P-type base region.
F. Nemati and J. D. Plummer have disclosed a two-device thyristor-based SRAM (T-RAM) cell that includes an access transistor and a gate-assisted, vertical PNPN thyristor, where the vertical thyristor is operated in a gate-enhanced switching mode. See F. Nemati and J. D. Plummer, A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories, Center for Integrated Systems, Stanford University, Stanford, Calif., 1999. The performance of the T-RAM cell depends on the turn-off characteristics of the vertical thyristor. The turn-off characteristics depend on the stored charge and carrier transit time in the P-type base region of the PNPN thyristor. By reverse biasing the thyristor for a write-zero operation and by using a gated electrode to assist with turn-off switching of the vertical thyristor to discharge the stored charge the turn-off characteristics for the vertical thyristor are improved from milliseconds to nanoseconds.
FIG. 1 is a circuit schematic 100 which illustrates an array of conventional thyristor-based Random Access Memory (T-RAM) cells including T-RAM cell 110.
As shown in FIG. 1, T-RAM cell 110 consists of word lines 120, 130, a common bit line 150, a Thin Capacitively-Coupled Thyristor (TCCT) device 160 in series with an NMOS access transistor 170. The TCCT device 160 provides an active storage element which comprises a thyristor 162 and a capacitor 165 coupled to the gate of the thyristor 162. The NMOS access transistor 170 is coupled between a cathode node 146 of the TCCT device 160 and the common bit line 150. An anode node 148 of the TCCT device 160 is fixed at a positive bias. The TCCT device 160 exhibits a bi-stable current-versus-voltage (I-V) characteristic. The bi-stable current-versus-voltage characteristic results in a wide read margin between logical one (1) and logical zero (0) data states because the on/off current ratio between two states are greater than 1×105. See F. Nemati et al. The bi-stable current-versus-voltage characteristic results in good read current because at a logical one (1) data state, the TCCT device 160 is in forward diode mode resulting in higher current. To store a logical one (1) in the T-RAM cell 110, a constant current greater than a standby or holding current is applied through the TCCT device 160 and the NMOS access transistor 170. The current from each of the memory cells is collected through the common bit line 150. During the read operation, the voltage level on the common bit line 150 must be maintained at a certain level (e.g., ground or one-half (Vdd)). If current flows from each of the memory cells connected to the common bit line 150, the voltage level on the common bit line 150 will fluctuate. This can cause the read operation to be disturbed (also referred to as a “read disturbance” problem) since the voltage level on the common bit line 150 is changed by both the selected cell as well as the amount of leakage current from the unselected cells.
FIG. 2 is a circuit schematic 200 which illustrates an array of conventional Thin Capacitively-Coupled Thyristor (TCCT)-DRAM cells including TCCT-DRAM cells 210, 270. In contrast to conventional DRAM cells, which usually include a MOSFET device and a capacitor, the TCCT-DRAM cell 210 consists of a single TCCT device 260 and three controls lines including a write enable line 230, word line 240, and a bit line 250. Notably, the TCCT-DRAM cell 210 does not require an access transistor. The TCCT device 260 consists of a thyristor 262 which includes an anode node 248 connected to the bit line 250, a cathode node 246 connected to the word line 240, and a gate capacitor 265 connected directly above a P-base region (not shown) of the thyristor 262 to a gate line which functions as the write enable line 230. The TCCT-DRAM cell 210 is operated using basic read/write operations which include a standby mode, a write logic one (1) operation, a write logic zero (0) operation, and a read operation.
In standby mode, both bit line 250 and word line 240 are at Vdd, and the stored data is maintained by a charge state of the P-base region of thyristor. The word line 240 in TCCT DRAM activates the TCCT cells connected along the write enable line 230. During a write logic one (1) operation, the voltage applied on the bit line 250 is kept high and the write enable line 230 is pulsed while word line 240 is held at ground level, triggering the TCCT device 260 to latch. The bias scheme for write zero (0) operation is the same as the write one (1) operation except that the voltage applied on the bit line 250 is kept low so that the pulsing of the write enable line 230 switches the TCCT device 260 into its blocking state. During a read operation, the word line 240 is held low and the change in the voltage or the current of the bit line 250 is read into a sense amplifier.
During a standby mode or “holding period,” which occurs after the write zero (0) operation, the P-base region (not shown) of the thyristor is negatively charged and the potential of the P-base region gradually increases due to a reverse leakage current that flows from the anode node 248 to the cathode node 246. Because of this leakage current the TCCT-DRAM cell 210 must be periodically refreshed during operation to reset the charge state of the TCCT-DRAM cell 210. The refresh operation involves reading a stored value from the TCCT-DRAM cell 210 and then writing the stored value back to the TCCT-DRAM cell 210.
Accordingly, there is a need for memory devices and memory cell structures which have a small memory cell size and fast operational speed, and for methods for fabricating such memory devices and memory cell structures. It would be desirable if such memory devices and memory cell structures can also eliminate the need to perform a periodic refresh operation. It would also be desirable if such memory devices and memory cell structures can reduce and/or eliminate problems such as read disturbance that can occur during read operations.